The subject system and method are generally directed to the selectively optimized adaptation of a memory controller for a memory device during power-on processing. More specifically, the subject system and method provide for control of power-on processing operations in selectively distributed manner, whereby one or more power-on processing operations are selectively actuated by portions of the system other than just the memory controller portion. Such operations as initialization and training may be selectively actuated by either the memory controller or a physical interface portion of the system.
Memory controllers are well known in the art. They are implemented as digital circuits dedicated to controlling/managing the flow of data written to and read from one or more memory devices, to which they are adapted as needed for properly calibrated operation therewith when initially powered on or periodically re-booted/re-started. Memory controllers may be suitably formed as separate devices or integrated with a central processing unit or other main controller, and serve the memory storage and access needs of various control or user application ‘master’ operations processed thereby. Memory controllers implement the logic necessary to read from and write to various types of solid state memory devices, examples of which include dynamic random access memory (DRAM), as well as electrically programmable types of non-volatile memory such as flash memory, and the like.
The particular operations required for power-on processing may vary depending on numerous factors applicable to a particular implementation of a given memory controller. These factors include among other things the type and configuration of the memory device to be accessed, parametric settings predefined for the particularly intended application, and requirements to be met for compliance with industry standards. As noted in following paragraphs, industry standards such as those established by the so-called Joint Electron Device Engineering Council (JEDEC) for semiconductor memory circuits and devices, for example, define operational specifications for certain power-on processing operations for memory controllers. Other industry standards, such as the so-called DFI (DDR PHY Interface) standard protocol defines the connectivity between a DDR-type source synchronous memory controller and a physical interface portion through which it communicates with DDR-type memory devices.
Historically, the initialization and training operations required to enable a memory controller to properly read and write data to a memory device through an intervening physical interface component were relegated exclusively to the memory controller for execution. The physical interface component remained generally passive. Although subjected to various configuring/calibrating processes during the required initialization and training, known physical interface components have not served to independently actuate any part of those initialization or training operations itself. While some physical interface components are known to have been expanded in function to ‘re-do’ certain restorative training, none have been provided with sufficient measures to provide independent actuation of initialization and/or training operations in connection with power-on processing of memory control systems. Nor has any memory controller been provided with sufficient measures to suitably interact with a physical interface component in that regard.
There is therefore a need for a memory controller system and method capable of selectively distributing actuation control for such operations required during power-on processing, while preserving compliance with applicable operational standards. There is also a need for a memory controller system and method which provides selective distribution of control over initialization and training operations in connection with power-on processing towards optimizing the efficiency and flexibility of adaption between a memory controller and a particular memory device.